LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Count_tb IS
END Count_tb;

ARCHITECTURE Count_tb_arch OF Count_tb IS

    COMPONENT Count IS
        PORT (
            -- CLOCK signal
            CLK : IN STD_LOGIC;
            -- RESET signal
            RST : IN STD_LOGIC
        );
    END COMPONENT;

    SIGNAL RST : STD_LOGIC;
    SIGNAL CLK : STD_LOGIC;

BEGIN

    U_Count : Count PORT MAP(CLK, RST);

    PROCESS
    BEGIN
        CLK <= '1';
        RST <= '0';
        WAIT FOR 10 ns;
        CLK <= '0';
        RST <= '1';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        CLK <= '1';
        WAIT FOR 10 ns;
        CLK <= '0';
        WAIT FOR 10 ns;
        FOR m IN 0 TO 600 LOOP
            FOR n IN 0 TO 50000000 LOOP
                CLK <= '1';
                WAIT FOR 10 ns;
                CLK <= '0';
                WAIT FOR 10 ns;
            END LOOP;
        END LOOP;

    END PROCESS;
END Count_tb_arch;